Propose, architect, and design RTL in Verilog for use in a mixed-signal integrated circuitContribute as part of a highly experienced team of engineers with extensive cross-functional skill setsApply clocking controls, FSM design, low power techniques, and high-speed design conceptsParticipate in design, architecture, and verification reviewsOversee digital backend design, including synthesis, static timing analysis, and logic equivalence checkingCreate documentation targeting design, verification, and test teamsAssist with the proposal, definition, documentation, and implementation of new featuresMentor and train junior engineers and New College Grad engineers